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E2B0028-27-Y2
Semiconductor MSM5298A
Semiconductor 68-DOT COMMON DRIVER
This version: MSM5298A Nov. 1997 Previous version: Mar. 1996
GENERAL DESCRIPTION
The MSM5298A is a dot matrix LCD common driver LSI which is fabricated using low power CMOS metal gate technology. This LSI consists of 68-bit bidirectional shift register, 68-bit level shifter and 68-bit 4-level driver. This LSI has 68 output pins to be connected to the LCD. By connecting two or more MSM5298As in series, this LSI is applicable to a wide LCD panel.
FEATURES
* Supply voltage : 4.5 to 5.5V * LCD driving voltage : 8 to 28V * Applicable LCD duty : 1/64 to 1/256 * Applicable segment driver : MSM5299A (80 outputs), MSM5299C (80 outputs) * Package options: 80-pin plastic QFP (QFP80-P-1420-0.80-K) (Product name : MSM5298AGS-K) 80-pin plastic QFP (QFP80-P-1420-0.80-BK) (Product name : MSM5298AGS-BK)
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Semiconductor
MSM5298A
BLOCK DIAGRAM
O 1 O2
O67 O68
V1 V2 V5 VEE VEE 68-Bit 4-Level Driver
VDD
DF DISP OFF
68-Bit Level Shifter VDD VSS 68-Bit Bidirectional Shift Register IO68
SHL IO1 CP
VDD VSS
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Semiconductor
MSM5298A
PIN CONFIGURATION (TOP VIEW)
O43 O42 O41 O40 O39 O38 O37 O36
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
O35 O34 O33 O32 O31 O30 O29 O28
O44 O45 O46 O47 O48 O49 O50 O51
1 2 3 4 5 6 7 8
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
O27 O26 O25 O24 O23 O22 O21 O20 O19 O18 O17 O16 O15 O14 O13 O12 O11 O10 O9 O8 O7 O6 O5 O4
O52 9 O53 10 O54 11 O55 12 O56 13 O57 14 O58 15 O59 16 O60 17 O61 18 O62 19 O63 20 O64 21 O65 22 O66 23 O67 24
O68 IO68 VEE V5 V2 V1 DISPOFF VDD SHL VSS DF CP
IO1 O1 O2
80-Pin Plastic QFP Note: The abbreviated part number "M5298A" is imprinted on the package surface.
O3
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Semiconductor
MSM5298A
ABSOLUTE MAXIMUM RATINGS
(VSS = 0 V) Parameter Supply Voltage (1) Supply Voltage (2) Input Voltage Storage Temperature Symbol VDD VLCD VI TSTG Condition Ta = 25C
Ta = 25C, VDD-VEE *1
Rating -0.3 to +6 0 to +30 -0.3 to VDD +0.3 -55 to +150
Unit V V V C
Ta = 25C --
*1 VDDV1>V2>V5>VEE
RECOMMENDED OPERATING CONDITIONS
(VSS = 0 V) Parameter Supply Voltage (1) Supply Voltage (2) Operating Temperature Symbol VDD VLCD Top Condition --
VDD-VEE
Range 4.5 to 5.5 *1 8 to 28 -20 to +85
Unit V V C
--
*1 VDDV1>V2>V5>VEE
ELECTRICAL CHARACTERISTICS
DC Characteristics
Parameter "H" Input Voltage "L" Input Voltage "H" Input Current "L" Input Current "H" Output Voltage "L" Output Voltage ON Resistance Supply Current Input Capacitance Symbol VIH VIL IIH IIL VOH VOL RON IDD CI
*1 *1 *1 *1 *2 *2 *4
(VDD = 5V10%, Ta = -20 to +85C) Condition -- -- VI = VDD, VDD = 5.5V VI= 0V, VDD = 5.5V IO= -0.4mA, VDD = 4.5V IO= 0.4mA, VDD = 4.5V VDD - VEE = 23V, VDD = 4.5V |VN - VO| = 0.25V fCP = 14kHz, VDD = 5.5V VDD - VEE = 23V, No load f = 1MHz
*3
Min. 0.8VDD VSS -- -- VDD - 0.4 -- -- -- --
Typ. -- -- -- -- -- -- 1.5 -- 5
Max. VDD 0.2VDD 1 -1 -- 0.4 3 100 --
Unit V V mA mA V V kW mA pF
*1 *2 *3 *4
Applicable to CP, IO1, IO68, SHL, DF, DISP OFF. Applicable to IO1, IO68. 14 1 VN = VDD to VEE, V2 = (VDD - VEE), V5 = (VDD - VEE), VDD = V1 15 15 Applicable to O1 to O68.
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Semiconductor Switching Characteristics
MSM5298A
(VDD = 5V10%, Ta = -20 to +85C, CL = 15pF) Parameter "H" , "L" Propagation Delay Time Clock Frequency Clock Pulse Width Data Setup Time IO1(IO68)AECP Data Hold Time CPAEIO1(IO68) Clock Pulse Rise/Fall Time Symbol tPLH tPHL fCP tW(CP) tSETUP tHOLD tr(CP) tf(CP) Condition -- -- -- -- -- -- Min. -- -- 125 100 100 -- Typ. -- -- -- -- -- -- Max. 250 1 -- -- -- 50 Unit ns MHz ns ns ns ns
tf(CP) tW(CP) CP 0.8VDD 0.8VDD tSETUP 0.2VDD tHOLD IO1 (IO68)
0.8VDD 0.8VDD 0.2VDD 0.2VDD
tr(CP)
0.8VDD 0.2VDD
tPLH tPHL IO68 (IO1) 0.8VDD 0.2VDD
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Semiconductor
MSM5298A
FUNCTIONAL DESCRIPTION
Pin Functional Description
* IO1, IO68, SHL
IO1 and IO68 are 68-bit bidirectional shift register input/output pins. The shifting direction is selected by the SHL pin. Refer to the table below.
SHL Shifting direction IO1/IO68 IO1 L O1 AE O68 IO68 Output Input/ output Input Description The scanning data from the LCD controller LSI is input into IO1 synchronized with the clock pulse.* 1 Shift register contents output pin. The data which is input into IO1 is output from IO68 with 68 bit's delay, synchronized with the clock pulse. The scanning data from the LCD controller LSI is input into IO68 synchronized with the clock pulse.* 1 Shift register contents output pin. The data which is input into IO68 is output from IO1 with 68 bit's delay, synchronized with the clock pulse.
IO68 H O68 AE O1 IO1
Input
Output
*1 The combination of the scanning data, IO1 or IO68, and the LCD driving output, O1 to O68, is shown in the table below.
IO1, IO68 "H" "L"
* CP
LCD driving output Select level (V1, VEE)
Non-select level (V2, V5)
Clock pulse input pin for 68-bit bidirectional shift register. The data is shifted to 68-bit bidirectional shift register at the falling edge of the clock pulse.
* DF
Alternate signal input pin for LCD driving.
* VDD, VSS
Supply voltage pins. VDD should be 4.5 to 5.5V. VSS is a ground pin. (VSS = 0V).
* DISP OFF
Control input pin for display data output level (O1 to O68). V1 level is output from O1 to O68 pin during "L" level input. Refer to Truth Table.
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Semiconductor
* V1, V2, V5, VEE
MSM5298A
Bias supply voltage pins to drive the LCD. The V1 pin can be separated from the VDD pin.
* O1 - O68
Display data output pins which correspond to each bit of the 68-bit bidirectional shift register. One of the four levels, V1, V2, V5 and VEE, is selected based on the combination of the latched data level and DF signal. (Refer to Truth Table.) Connect these outputs to the common side of the LCD panel. Truth Table
DF L L H H X Shift register data L H L H X DISP OFF H H H H L Driver output level (O1 to O68) V2 VEE V5 V1 V1
X : Don't care
NOTES ON USE (when turning the power ON or OFF)
The LCD drivers of this IC require a high voltage. For this reason, if a high voltage is applied to the LCD drivers with the logic power supply floating, excess current flows. This may damage the IC. Be sure to follow the sequence below when turning the power ON or OFF. Power ON : Logic circuits ON AE LCD drivers ON, or both ON at a time Power OFF : LCD drivers OFF AE logic circuits OFF, or both OFF at a time
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Semiconductor
MSM5298A
PACKAGE DIMENSIONS
(Unit : mm)
QFP80-P-1420-0.80-K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 1.27 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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Semiconductor
MSM5298A
(Unit : mm)
QFP80-P-1420-0.80-BK
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 1.27 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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